Intel(R) Xeon(R) 6 processors when using Intel(R) TDX

CVE-2025-31936
HIGH 7.0

At a glance

Source
NVD
EPSS
EPSS 0.10 % · percentile 1 ()
State
PUBLISHED
Published
Updated
Assigner
intel
NVD status
Analyzed

Description

Improper handling of overlap between protected memory ranges for some Intel(R) Xeon(R) 6 processors when using Intel(R) TDX within SMM may allow an escalation of privilege. SMM adversary with a privileged user combined with a high complexity attack may enable escalation of privilege. This result may potentially occur via local access when attack requirements are present with special internal knowledge and requires no user interaction. The potential vulnerability may impact the confidentiality (high), integrity (high) and availability (none) of the vulnerable system, resulting in subsequent system confidentiality (none), integrity (none) and availability (none) impacts.

Weaknesses (CWE)

  • CWE-1260 — Improper Handling of Overlap Between Protected Memory Ranges

References

Scores

VersionScoreVectorScored by
CVSS 4.0HIGH 7.0CVSS:4.0/AV:L/AC:H/AT:P/PR:H/UI:N/VC:H/VI:H/VA:N/SC:N/SI:N/SA:Nintel
CVSS 4.0HIGH 7.0CVSS:4.0/AV:L/AC:H/AT:P/PR:H/UI:N/VC:H/VI:H/VA:N/SC:N/SI:N/SA:N/E:X/CR:X/IR:X/AR:X/MAV:X/MAC:X/MAT:X/MPR:X/MUI:X/MVC:X/MVI:X/MVA:X/MSC:X/MSI:X/MSA:X/S:X/AU:X/R:X/V:X/RE:X/U:XNVD · secure@intel.com (Secondary)
CVSS 3.1MEDIUM 5.7CVSS:3.1/AV:L/AC:H/PR:H/UI:N/S:U/C:H/I:H/A:NNVD · nvd@nist.gov (Primary)

European references

CERT-FR advisories

Affected configurations (NVD CPE)

Affected products

ProductVersions
Intel(R) Xeon(R) 6 processors when using Intel(R) TDXaffected See references

Sources

SourceLicence
CVE List (CVEProject cvelistV5)CVE Program Terms of Use
EPSS (FIRST.org)FIRST — attribution requested
ENISA EUVDENISA — reproduction authorised, source acknowledged
CERT-FR (ANSSI)Licence Ouverte / Etalab 2.0
NVD (NIST) via fkie-cad/nvd-json-data-feedsPublic domain — this product uses data from the NVD API but is not endorsed or certified by the NVD