Intel(R) Processor

CVE-2024-24853
HIGH 7.3

At a glance

Source
NVD
EPSS
EPSS 0.23 % · percentile 14 ()
State
PUBLISHED
Published
Updated
Assigner
intel
NVD status
Deferred

Description

Incorrect behavior order in transition between executive monitor and SMI transfer monitor (STM) in some Intel(R) Processor may allow a privileged user to potentially enable escalation of privilege via local access.

Weaknesses (CWE)

  • CWE-696 — Incorrect Behavior Order

References

Scores

VersionScoreVectorScored by
CVSS 4.0HIGH 7.3CVSS:4.0/AV:L/AC:H/AT:P/PR:H/UI:P/VC:H/VI:H/VA:H/SC:H/SI:H/SA:Hintel
CVSS 3.1HIGH 7.2CVSS:3.1/AV:L/AC:H/PR:H/UI:R/S:C/C:H/I:H/A:Hintel
CVSS 4.0HIGH 7.3CVSS:4.0/AV:L/AC:H/AT:P/PR:H/UI:P/VC:H/VI:H/VA:H/SC:H/SI:H/SA:H/E:X/CR:X/IR:X/AR:X/MAV:X/MAC:X/MAT:X/MPR:X/MUI:X/MVC:X/MVI:X/MVA:X/MSC:X/MSI:X/MSA:X/S:X/AU:X/R:X/V:X/RE:X/U:XNVD · secure@intel.com (Secondary)
CVSS 3.1HIGH 7.2CVSS:3.1/AV:L/AC:H/PR:H/UI:R/S:C/C:H/I:H/A:HNVD · secure@intel.com (Secondary)

European references

CERT-FR advisories

Affected products

ProductVersions
Intel(R) Processoraffected See references

Sources

SourceLicence
CVE List (CVEProject cvelistV5)CVE Program Terms of Use
EPSS (FIRST.org)FIRST — attribution requested
ENISA EUVDENISA — reproduction authorised, source acknowledged
CERT-FR (ANSSI)Licence Ouverte / Etalab 2.0
NVD (NIST) via fkie-cad/nvd-json-data-feedsPublic domain — this product uses data from the NVD API but is not endorsed or certified by the NVD