Intel(R) FPGA SDK for OpenCL(TM) software technology
At a glance
- Source
- NVD
- EPSS
- EPSS 0.15 % · percentile 4 ()
- State
- PUBLISHED
- Published
- Updated
- Assigner
- intel
- NVD status
- Analyzed
Description
Uncontrolled search path in some Intel(R) FPGA SDK for OpenCL(TM) software technology may allow an authenticated user to potentially enable escalation of privilege via local access.
Weaknesses (CWE)
- CWE-427 — Uncontrolled Search Path Element
References
Scores
| Version | Score | Vector | Scored by |
|---|---|---|---|
| CVSS 4.0 | MEDIUM 5.4 | CVSS:4.0/AV:L/AC:H/AT:P/PR:L/UI:A/VC:H/VI:H/VA:H/SC:N/SI:N/SA:N | intel |
| CVSS 3.1 | MEDIUM 6.7 | CVSS:3.1/AV:L/AC:H/PR:L/UI:R/S:U/C:H/I:H/A:H | intel |
| CVSS 4.0 | MEDIUM 5.4 | CVSS:4.0/AV:L/AC:H/AT:P/PR:L/UI:A/VC:H/VI:H/VA:H/SC:N/SI:N/SA:N/E:X/CR:X/IR:X/AR:X/MAV:X/MAC:X/MAT:X/MPR:X/MUI:X/MVC:X/MVI:X/MVA:X/MSC:X/MSI:X/MSA:X/S:X/AU:X/R:X/V:X/RE:X/U:X | NVD · secure@intel.com (Secondary) |
| CVSS 3.1 | MEDIUM 6.7 | CVSS:3.1/AV:L/AC:H/PR:L/UI:R/S:U/C:H/I:H/A:H | NVD · secure@intel.com (Secondary) |
| CVSS 3.1 | HIGH 7.8 | CVSS:3.1/AV:L/AC:L/PR:L/UI:N/S:U/C:H/I:H/A:H | NVD · nvd@nist.gov (Primary) |
European references
- ENISA EUVD · EUVD-2024-21339
- GCVE · GCVE-0-2024-23909
CERT-FR advisories
- CERTFR-2024-AVI-0679 — Multiples vulnérabilités dans les produits Intel · cert.ssi.gouv.fr
Affected configurations (NVD CPE)
cpe:2.3:a:intel:field_programmable_gate_array_software_development_kit_for_opencl:13.0:-:*:*:pro:*:*:*cpe:2.3:a:intel:field_programmable_gate_array_software_development_kit_for_opencl:13.0:-:*:*:standard:*:*:*cpe:2.3:a:intel:field_programmable_gate_array_software_development_kit_for_opencl:13.0:sp1:*:*:pro:*:*:*cpe:2.3:a:intel:field_programmable_gate_array_software_development_kit_for_opencl:13.0:sp1:*:*:standard:*:*:*cpe:2.3:a:intel:field_programmable_gate_array_software_development_kit_for_opencl:13.1:*:*:*:pro:*:*:*cpe:2.3:a:intel:field_programmable_gate_array_software_development_kit_for_opencl:13.1:*:*:*:standard:*:*:*cpe:2.3:a:intel:field_programmable_gate_array_software_development_kit_for_opencl:14.0:*:*:*:pro:*:*:*cpe:2.3:a:intel:field_programmable_gate_array_software_development_kit_for_opencl:14.0:*:*:*:standard:*:*:*cpe:2.3:a:intel:field_programmable_gate_array_software_development_kit_for_opencl:14.1:*:*:*:pro:*:*:*cpe:2.3:a:intel:field_programmable_gate_array_software_development_kit_for_opencl:14.1:*:*:*:standard:*:*:*cpe:2.3:a:intel:field_programmable_gate_array_software_development_kit_for_opencl:15.0:*:*:*:pro:*:*:*cpe:2.3:a:intel:field_programmable_gate_array_software_development_kit_for_opencl:15.0:*:*:*:standard:*:*:*cpe:2.3:a:intel:field_programmable_gate_array_software_development_kit_for_opencl:15.1:*:*:*:pro:*:*:*cpe:2.3:a:intel:field_programmable_gate_array_software_development_kit_for_opencl:15.1:*:*:*:standard:*:*:*cpe:2.3:a:intel:field_programmable_gate_array_software_development_kit_for_opencl:16.0:*:*:*:pro:*:*:*cpe:2.3:a:intel:field_programmable_gate_array_software_development_kit_for_opencl:16.0:*:*:*:standard:*:*:*cpe:2.3:a:intel:field_programmable_gate_array_software_development_kit_for_opencl:16.1:*:*:*:pro:*:*:*cpe:2.3:a:intel:field_programmable_gate_array_software_development_kit_for_opencl:16.1:*:*:*:standard:*:*:*cpe:2.3:a:intel:field_programmable_gate_array_software_development_kit_for_opencl:17.0:*:*:*:pro:*:*:*cpe:2.3:a:intel:field_programmable_gate_array_software_development_kit_for_opencl:17.0:*:*:*:standard:*:*:*cpe:2.3:a:intel:field_programmable_gate_array_software_development_kit_for_opencl:17.1:*:*:*:pro:*:*:*cpe:2.3:a:intel:field_programmable_gate_array_software_development_kit_for_opencl:17.1:*:*:*:standard:*:*:*cpe:2.3:a:intel:field_programmable_gate_array_software_development_kit_for_opencl:18.0:*:*:*:pro:*:*:*cpe:2.3:a:intel:field_programmable_gate_array_software_development_kit_for_opencl:18.0:*:*:*:standard:*:*:*cpe:2.3:a:intel:field_programmable_gate_array_software_development_kit_for_opencl:18.1:*:*:*:pro:*:*:*cpe:2.3:a:intel:field_programmable_gate_array_software_development_kit_for_opencl:18.1:*:*:*:standard:*:*:*cpe:2.3:a:intel:field_programmable_gate_array_software_development_kit_for_opencl:19.1:*:*:*:pro:*:*:*cpe:2.3:a:intel:field_programmable_gate_array_software_development_kit_for_opencl:19.1:*:*:*:standard:*:*:*cpe:2.3:a:intel:field_programmable_gate_array_software_development_kit_for_opencl:19.2:*:*:*:pro:*:*:*cpe:2.3:a:intel:field_programmable_gate_array_software_development_kit_for_opencl:19.3:*:*:*:pro:*:*:*cpe:2.3:a:intel:field_programmable_gate_array_software_development_kit_for_opencl:19.4:*:*:*:pro:*:*:*
Affected products
| Product | Versions |
|---|---|
| Intel(R) FPGA SDK for OpenCL(TM) software technology | affected See references |
Sources
| Source | Licence |
|---|---|
| CVE List (CVEProject cvelistV5) | CVE Program Terms of Use |
| EPSS (FIRST.org) | FIRST — attribution requested |
| ENISA EUVD | ENISA — reproduction authorised, source acknowledged |
| CERT-FR (ANSSI) | Licence Ouverte / Etalab 2.0 |
| NVD (NIST) via fkie-cad/nvd-json-data-feeds | Public domain — this product uses data from the NVD API but is not endorsed or certified by the NVD |